1. Field of the Invention
The invention relates to the field of wafer scale integration.
2. Prior Art
In the fabrication of integrated circuits such as metal-oxide-silicon (MOS) integrated circuits, a plurality of identical circuits such as memories are simultaneously fabricated on a wafer. The wafer is then broken along scribe lines into a plurality of dice or chips which are separately tested and packaged. Typically, yields from a given wafer are less than a 100 percent and many of the chips are discarded. This fabrication technique has several disadvantages. For example it is recognized in the semiconductor industry that the cost associated with the packaging of the individual chips represents a substantial portion of the total costs of the end products. Moreover, the wafer area is not economically used since substantial area is needed for scribe lines and bonding pads. Many attempts have been made in the prior art to utilize the useful or operative circuits on a wafer while bypassing the inoperative circuits without physically separating the chips. For a general discussion of this technology, see the prior art section of U.S. Pat. No. 3,641,661.
Generally, the operative circuits or devices on a wafer are electrically isolated from the inoperative devices through the use of one or more discretionary connection. For example, after a device is tested on the wafer, and is found to be operative, it is connected to a wafer bus or master circuit. Among the prior art techniques used for discretionary connections include those which utilize specially generated masks, for example, see U.S. Pat. No. 3,835,530; or fuses, fuseable links, or the like, for example see U.S. Pat. No. 3,810,301.
As will be seen, the present invention requires only a single discretionary connection for electrically connecting a circuit or device to a wafer bus even where each device comprises an entire memory system, such as a 4K bit random-access memory (RAM).